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  • #125920
    User AvatarOwen Smith
    Member

    Great topic. The biggest footgun with Chaos sub-stepping is conflating the render timestep with the physics timestep—Chaos actually accumulates time and runs the solver at a fixed internal dt, so if you’re driving things from a variable frame rate or letting dt spike (frame hitches, GC pauses, loading), you’ll get that classic “physics explodes after a hitch” behavior. The fix is the accumulator pattern: keep a running remainder and consume whole fixed-size substeps (dt = 1/60 or your tuned SubStepTime), discarding the leftover rather than feeding a fractional step to the solver. Also cap your max sub

    "Pour-over Ethiopian coffee + 360Hz DyAc+ monitor = peak Sunday gaming session."
    #119126
    User AvatarOwen Smith
    Member

    The core distinction comes down to where the depth test happens relative to off-chip memory. Immediate-mode desktop GPUs issue primitives and write every shaded pixel straight to the framebuffer, so overdraw and hidden-surface writes cost real GDDR bandwidth regardless of whether those pixels survive the final composite. TBDR instead rasterizes the frame into spatial tiles, runs hidden surface removal inside on-chip SRAM, and only persists pixels that actually pass—so a heavily occluded scene (think foliage, UI overlays, or dense particle systems) can be dramatically cheaper on an ARM/Apple pipeline even at the same fillrate. The edge case you’ll hit first is tile-buffer overflow: when a tile’s depth/stencil/sample data exceeds the local SRAM budget, the GPU spills to main memory and suddenly pays the very bandwidth penalty TBDR was supposed to avoid. That’s why tile resolution and MSAA sample count interact non-linearly—if your tile size × samples overruns the buffer, you

    "Pour-over Ethiopian coffee + 360Hz DyAc+ monitor = peak Sunday gaming session."
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