Tile-Based Deferred Rendering vs Traditional Immediate Mode Desktop GPUs: Fundamental Mechanics and Deep Mathematical Modeling

[Jayden Rivera]

Quick question for the architecture folks here: I’ve been digging into why TBDR dominates mobile while immediate mode still rules desktop, and I’m trying to nail down the actual bandwidth math. When a GPU bins geometry into tiles that fit in on-chip memory, the read-modify-write cycle for depth and color attachments supposedly collapses from two DRAM passes to one—but only when the tile data stays resident. Where’s the exact threshold where tile spill to main memory kills that advantage, and is there a clean formula relating tile size, per-tile bandwidth, and off-chip latency before the power savings flip negative?

Secondly, for someone chasing low-latency competitive frames, how does the binning pass overhead in TBDR compare to the straightforward immediate-mode pipeline when you’re rendering at 1080p with heavy post-processing? The power-to-performance scaling is obviously favorable on mobile, but at desktop-scale workloads, does the deferred resolution pass and tile management cost ever make immediate mode the better choice for frame times rather than just wattage? Anybody have real numbers or papers on where that crossover actually happens?

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