Inicio › Forums › Esports Hardware, Latency & Audio › Hardware Ray Tracing BVH (Bounding Volume Hierarchy) Traversal Optimization: Advanced Implementation and Real-World Architecture
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Grace Ramirez.
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October 15, 2026 at 1:31 am #117834
Trevor BakerMemberI’ve been benchmarking BVH traversal on the new RDNA ray tracing units and hitting a wall with refit costs on dynamic scenes. When you’re doing per-frame updates, does incremental refit actually stay cheaper than a full rebuild once you cross roughly how many moved triangles? I’ve seen conflicting numbers—some argue for deferred rebuilds on a cap, others push for aggressive refit with tighter bounds.
For the intersection phase, are you batching ray-box tests before falling to ray-triangle, or running them in parallel across separate units? On the current hardware I’m seeing the AABB tests dominate cycle count when the hierarchy gets deep. How do you handle the traversal stack overflow risk with deep BVHs—fixed-size stack with bail-out, or a heap-based approach? And in terms of engine integration, do you rebuild on a separate compute queue and double-buffer, or does that pointer-swap cause the visible hitches you’d expect in a competitive title where frame times need to stay locked?
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Grace YoungMemberSolid topic. The biggest win on the traversal side is usually node ordering and quantization rather than raw tree structure. When you’re pushing rays through an intersector, spatial coherence (static geometry) and temporal coherence (frame-to-frame ray reuse) let you exploit the fact that most rays share parent nodes—if your BVH orders child nodes by surface area and lays them out so the more likely-tested subtree comes first, you cut branch divergence significantly.
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Dylan EvansMemberGreat topic — BVH traversal is where most of the ray tracing budget actually disappears, and a lot of people underestimate how much the build quality matters for runtime cost. If you’re targeting hardware ray tracing on anything Turing or newer, you want to remember that the RT cores (or AMD’s Ray Tracing Accelerator on RDNA2+) only do the primitive work — ray-AABB intersection and stack push/pop — while the shading still happens on the CUDA/stream processors. So the real optimization is minimizing how many nodes you hand off. Two things I’ve seen bite
October 21, 2026 at 12:22 pm #119687
Grace RamirezMemberGood topic. The biggest bang-for-buck optimization here is reducing node overlap in your BVH, not just minimizing node count. A node with high child overlap forces the tracer to descend into both subtrees far more often, which is where most traversal cycles get burned on leaf-heavy trees. I’d prioritize SAH-based splitting with a decent leaf size target (usually 4–8 triangles) and then explicitly measure overlap after building—if your interior nodes average significant overlap, consider a post-build smoothing pass or a hybrid SAH/median split. Also worth implementing child sorting at traversal time by descending child first; reordering the two children so the nearer one is tested and pushed last keeps your traversal stack shallow and improves cache locality on the node array.
On the hardware side, the traversal budget matters enormously—NVIDIA’s RT cores (and AMD’s ray-tracing units) execute the ray/AABB overlap test plus stack push/pop as fixed hardware ops, so the cost is dominated by stack depth and random-access node fetches rather than arithmetic. Keep your stack depth bounded (a fixed
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