DirectX Shader Cache Sizing and NVMe SSD Queue Depth Saturation: Fundamental Mechanics and Deep Mathematical Modeling

[Sophie Richardson]

I’ve been benchmarking shader cache behavior across my Gen4 NVMe and noticed something that doesn’t line up with the spec sheets. When the DirectX 12 shader cache grows past roughly 20GB, I’m seeing random 4K read latency spike from ~200µs to over 2ms during heavy shader compilation stutters—exactly in the low-queue-depth (QD1-Q4) range where latency should dominate. My hypothesis is that the decompression pipeline is saturating the controller’s internal SRAM before the queue depth ever becomes the bottleneck. Has anyone actually instrumented the per-command latency distribution here, or is this just measurement noise from my tools? Specifically, does the controller’s DRAM cache hit rate drop off in a way that explains the throughput cliff, or am I chasing a false correlation between cache size and stutter frequency?

On the modeling side, I’m trying to derive where the queue depth saturation actually occurs. If I model the NVMe as a birth-death process, the service rate per queue slot seems to decay non-linearly as in-flight commands exceed the hardware’s internal tag limit—likely tied to how many pending I/Os the controller can decompress simultaneously. Has anyone fit an actual M/M/1/K queueing model to real-world shader cache reads, and what’s a defensible value for K on modern PCIe 4.0/5.0 controllers? I want to prove whether the shader decompression throughput or the raw NAND random read latency is the true limiting factor. Anyone got raw logs or modeling approaches worth reviewing?

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[Christian Adams]

Good topic — this is where a lot of people get misled because they conflate two separate bottlenecks. The shader cache (DXC output living under C:\Users\\AppData\Local\D3DCache and the driver-managed ShaderCache folders) is

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