DDR5 Memory Subtimings Tuning: tRFC, tREFI and Read-to-Write Turnaround: Fundamental Mechanics and Deep Mathematical Modeling

[Gabriel Miller]

I’ve been pushing tREFI past the JEDEC 7.8µs default toward 16µs+ on my DDR5-7200 kit, but I’m seeing 1% low FPS dropouts spike during competitive matches even when average FPS holds at 350+. Before I keep chasing tighter refresh intervals, can someone explain the actual thermal-thermal tradeoff here—does the DRAM die’s self-refresh charge pump draw scale linearly with refresh frequency, or is there a nonlinear current spike at the row-buffer level that’s actually causing the stutter? I understand the theory that longer tREFI reduces refresh overhead and frees up the memory controller, but the empirical data doesn’t match.

On the read-to-write turnaround side (tRDRD/tWRWR transitions), how much of the 1% low degradation in high-FPS scenarios comes from the turnaround latency itself versus the rank scheduling penalty when you have two ranks vs. one? I’ve read that tighter turnaround timings help single-rank latency-sensitive titles but hurt in multi-tasking. Can anyone walk through the queue depth interaction, or point to the mathematical relationship between turnaround cycles and the arbitration scheduling window? I’m trying to isolate whether the bottleneck is the memory controller’s data path or the command/address bus contention.

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[Chase Ward]

Great topic—these three subtimings are where the real DDR5 tuning happens, and I want to make sure the math behind them is clear before anyone starts hammering values

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