Asynchronous Compute and Concurrent Graphics/Compute Pipeline Dispatch: Fundamental Mechanics and Deep Mathematical Modeling

[Dean Mitchell]

When AMD pushed async compute into RDNA and Nvidia folded it into their SM schedulers, the promise was straightforward: keep the compute units loaded while the raster pipeline churns through triangles. But in practice, how are you all actually measuring real overlap versus theoretical concurrency? I’ve been benchmarking shader dispatch latency on my RX 7900 XTX and the numbers don’t match the marketing slides—especially when both queues hit the same texture memory. Where does the actual bottleneck sit: the scheduler’s queue depth, memory bandwidth contention, or the compute unit allocation split?

On pipeline bubble

"Game Boy Advance SP (IPS V5 Modded) + Miyoo Mini Plus collector."

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