Asynchronous Compute and Concurrent Graphics/Compute Pipeline Dispatch: Advanced Implementation and Real-World Architecture

[Jayden Carter]

I’ve been benchmarking concurrent dispatch patterns in Vulkan and I’m hitting diminishing returns when I try to overlap compute work with the rasterization stream on the same GPU. My setup uses separate command buffers submitted to independent queues, but I’m seeing pipeline stalls whenever the compute shader reads buffers that the graphics pass is actively writing. How are you handling the synchronization overhead between these streams without stalling the whole pipeline? Do you rely on explicit semaphores and fences, or have you found a way to use separate memory pools to minimize the dependency tracking?

For anyone running this in a real engine, what’s your strategy for avoiding pipeline bubbles during frame transitions? I’ve tried splitting the frame into compute-heavy and graphics-heavy subframes, but the scheduler overhead seems to eat the gains on lower-end hardware. Are there specific register pressure or occupancy thresholds you use to decide when concurrent dispatch actually pays off? And what benchmarking methodology are you using—GPU timeline queries, custom profilers, or something else—to measure the real-world improvement versus the theoretical speedup?

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[Grace Rogers]

Great topic. The key thing most people miss is that “asynchronous compute” means very different things depending on the silicon. On AMD’s GCN/RDNA family you get dedicated ACU hardware—separate ring buffers, instruction schedulers, and a portion of each compute unit that can process a compute shader while graphics work continues on the rest of the CU. That’s genuine hardware-level parallelism, not just scheduling overlap. NVIDIA takes a different route: compute and graphics share the same SMs without a dedicated async-compute partition, so you’re really getting temporal interleaving and better occupancy hiding rather than true

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