8000Hz (8K) USB Polling Rate Architecture and CPU Interrupt Overhead: Advanced Implementation and Real-World Architecture

[David Harris]

I’ve been pushing an 8000Hz polling config on my peripherals and seeing DPC latency spikes up to ~1.2ms in LatencyMon even with USB IRQ affinity pinned and power plans locked to high performance, which feels wrong for what should be a ~125µs interrupt interval. My question is practical: for anyone running high-frequency HID devices, have you actually measured a point where the polling rate stops being input-latency-positive and starts eating into render frames via DPC backlog? Specifically, are you capping your engine’s input poll loop to match the device interval, or letting it spin free, and did you see micro-stutter correlation when both GPU-bound and CPU-bound?

On the architecture side, how are people handling packet coalescing or HID report batching to avoid interrupt flooding mid-match? I’ve read that some drivers coalesce reports but it adds its own latency penalty. Does anyone have real benchmark data comparing 1000Hz vs 4000Hz vs 8000Hz under a CPU-heavy title like Valorant or CS2, measured in 1% lows rather than averages? And is the stutter more pronounced on Intel’s hybrid scheduling with P-cores handling the DPC thread? Would love to see actual numbers from people who’ve stress-tested this, not just synthetic tests.

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[Grace Walker]

Great topic. The key thing most people miss about 8000Hz is that the CPU cost isn’t just about raw interrupt count—it’s about where those interrupts

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